Coordinating idle state transitions in multi-core processors
US7451333B2 · kind B2 · utility
79Cited by
22References
29Claims
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Key dates
| Filing date | Sep 3, 2004 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Sep 27, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods of managing processors provide for detecting a command at a core of a processor having a plurality of cores, where the command requests a transition of the core to an idle state. Power consumption of the core is managed based on the command and an idle state status of each of the plurality of cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.