Circuit for compression and storage of circuit diagnosis data
US7451373B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2006 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Sep 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31813
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H matrix XOR gates arranged as a switching mechanism between the test data inputs and the test data outputs such that data applied to the test data inputs is produced at the test data outputs compressed in accordance with coefficients of an H matrix of an error-correcting code, and compensation XOR gates arranged between the test data inputs and the test data outputs, each compensation XOR gate including an input for receiving a compensation value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.