Speeding up timing analysis by reusing delays computed for isomorphic subcircuits
US7451412B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2005 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Aug 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that speeds up timing analysis by reusing delays computed for isomorphic subcircuit. During operation, the system receives a circuit block to be analyzed, wherein the circuit block is in the form of a netlist. The system then subdivides the circuit block into a set of subcircuits. The subcircuits are then partitioned into equivalence classes, which contain subcircuits which are topologically isomorphic to each other. Next, the system performs a timing analysis by tracing paths through a timing graph for the circuit block. During this timing analysis, whenever a delay is required for a subcircuit, the system determines if a corresponding delay has been already computed for the equivalence class associated with the subcircuit. If so, the system reuses the delay. If not, the system computes the delay for the subcircuit, and then associates the computed delay with the equivalence class so that the computed delay can be reused for isomorphic subcircuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.