Bus representation for efficient physical synthesis of integrated circuit designs
US7451427B2 · kind B2 · utility
4Cited by
7References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 13, 2006 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Jan 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for the abstraction of connectivity that provides an intermediate data path representation of integrated circuit (IC) designs is provided. The connectivity abstraction maintains the compactness of a bus level representation as well as the uniqueness of a bit level representation. Connectivity abstraction significantly reduces network complexity, i.e., the number of wires in a design and the execution time of physical synthesis of IC designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.