Method of manufacturing a flash memory device
US7452773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2006 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | May 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/43
Abstract
In a method of manufacturing a flash memory device, an insulation layer pattern is formed on a substrate having cell and peripheral regions. Trenches formed in the substrate are converted into trench structures. A tunnel oxide layer is formed on the substrate. A space between the trench structures is filled with a first conductive layer. The trench structures are removed to form trench isolation structures and to convert the first conductive layer into a first conductive layer pattern. A dielectric layer is formed on the first conductive layer patterns and the trench isolation structures. An insulation layer is formed on the substrate in the peripheral region. A third conductive layer is formed on the second conductive layer, the insulation layer and the trench isolation layers. First and second gate structures are formed in the cell region and the peripheral region, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.