Sung-Un Kwon
20Patents
4h-index
37Co-inventors
59Inventor score
Filing activity: Jun 4, 2004 → Feb 5, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8507353B2 | Method of forming semiconductor device having self-aligned plug | Electricity | 34 | Active |
| US9490256B2 | Semiconductor devices having contact plugs overlapping associated bitline structures and contact holes and method of manufacturing the same | Electricity | 6 | Active |
| US8790976B2 | Method of forming semiconductor device having self-aligned plug | Electricity | 5 | Active |
| US7777265B2 | Semiconductor device having contact barrier and method of manufacturing the same | Emerging Cross-Sectional Technologies | 4 | Active |
| US7452773B2 | Method of manufacturing a flash memory device | Electricity | 3 | Active |
| US8158445B2 | Methods of forming pattern structures and methods of manufacturing semiconductor devices using the same | Electricity | 3 | Active |
| US8133757B2 | Method of manufacturing a phase changeable memory unit having an enhanced structure to reduce a reset current | Electricity | 2 | Active |
| US10573653B2 | Semiconductor devices having contact plugs overlapping associated bitline structures and contact holes | Electricity | 1 | Active |
| US8772121B2 | Phase change memory devices and methods of manufacturing the same | Electricity | 1 | Active |
| US9786672B2 | Method of manufacturing semiconductor devices having contact plugs overlapping associated bitline structures and contact holes | Electricity | 1 | Active |
| US7659162B2 | Phase change memory device and method of manufacturing the same | Electricity | 1 | Active |
| US7498253B2 | Local interconnection method and structure for use in semiconductor device | Electricity | 0 | Active |
| US7989279B2 | Method of fabricating semiconductor device | Electricity | 0 | Active |
| US7531450B2 | Method of fabricating semiconductor device having contact hole with high aspect-ratio | Electricity | 0 | Active |
| US10177155B2 | Method of manufacturing semiconductor devices having contact plugs overlapping associated bitline structures and contact holes | Electricity | 0 | Active |
| US10700074B2 | Semiconductor devices | Electricity | 0 | Active |
| US8361849B2 | Method of fabricating semiconductor device | Electricity | 0 | Active |
| US10446558B2 | Method of manufacturing semiconductor devices having contact plugs overlapping associated bitline structures and contact holes | Electricity | 0 | Active |
| US7202163B2 | Local interconnection method and structure for use in semiconductor device | Electricity | 0 | Expired |
| US9754785B2 | Methods of manufacturing semiconductor devices | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.