Method for applying a stress layer to a semiconductor device and device formed therefrom
US7453107B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 4, 2007 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | May 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
Abstract
A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state. A gate region is also formed in the substrate and doped with a second type of impurities. The gate region abuts a channel region of the conducting region. A stress layer is deposited on at least a portion of the conducting region. The stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.