DSM Solutions, Inc.
20Patents
20Active
20Granted
50Portfolio score
Filing activity: Oct 28, 2005 → Nov 14, 2008 · 20 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7453107B1 | Method for applying a stress layer to a semiconductor device and device formed therefrom | Electricity | 15 | Active |
| US7592841B2 | Circuit configurations having four terminal JFET devices | Electricity | 14 | Active |
| US7569873B2 | Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys | Electricity | 9 | Active |
| US7560755B2 | Self aligned gate JFET structure and method | Electricity | 8 | Active |
| US7525163B2 | Semiconductor device, design method and structure | Emerging Cross-Sectional Technologies | 6 | Active |
| US7525136B2 | JFET device with virtual source and drain link regions and method of fabrication | Electricity | 6 | Active |
| US7633784B2 | Junction field effect dynamic random access memory cell and content addressable memory cell | Physics | 5 | Active |
| US7629812B2 | Switching circuits and methods for programmable logic devices | Electricity | 5 | Active |
| US7557393B2 | JFET with built in back gate in either SOI or bulk silicon | Electricity | 4 | Active |
| US7474125B2 | Method of producing and operating a low power junction field effect transistor | Electricity | 4 | Active |
| US7645654B2 | JFET with built in back gate in either SOI or bulk silicon | Electricity | 3 | Active |
| US7531854B2 | Semiconductor device having strain-inducing substrate and fabrication methods thereof | Electricity | 2 | Active |
| US7605031B1 | Semiconductor device having strain-inducing substrate and fabrication methods thereof | Electricity | 2 | Active |
| US7642566B2 | Scalable process and structure of JFET for small and decreasing line widths | Electricity | 2 | Active |
| US7525138B2 | JFET device with improved off-state leakage current and method of fabrication | Electricity | 2 | Active |
| US7648898B2 | Method to fabricate gate electrodes | Electricity | 1 | Active |
| US7645662B2 | Transistor providing different threshold voltages and method of fabrication thereof | Electricity | 1 | Active |
| US7633101B2 | Oxide isolated metal silicon-gate JFET | Electricity | 0 | Active |
| US7694069B2 | System and method for detecting multiple matches | Physics | 0 | Active |
| US7646233B2 | Level shifting circuit having junction field effect transistors | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.