Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof
US7453113B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2007 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Apr 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
Abstract
A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.