Early high speed serializer-deserializer (HSS)internal receive (Rx) interface for data sampling clock signals on parallel bus
US7454543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2006 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Mar 31, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a method for reading data from a serial data source in a parallel format, data from the serial data source is deserialized by placing a plurality of predefined units of data onto a parallel bus and asserting a deserialization clock when each of the plurality of predefined units is valid on the parallel bus. A delayed clock pulse is generated a predetermined amount of time after each assertion of the deserialization clock. Each delayed pulse is repeated so as to generate an end point repeated clock pulse corresponding to each delayed pulse wherein the predetermined amount of time is an amount of time that ensures that each predefined unit of data on the parallel bus is valid when each end point repeated clock pulse is asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.