Architecture and control of reed-solomon list decoding
US7454690B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2005 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Jan 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4146
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.