Gregory Burd
328Patents
30h-index
59Co-inventors
93Inventor score
Filing activity: Oct 31, 2000 → Nov 7, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7184486B1 | LDPC encoder and decoder and method thereof | Electricity | 204 | Expired |
| US7752523B1 | Reduced-complexity decoding of parity check codes | Electricity | 156 | Active |
| US7685494B1 | Error correction coding for varying signal-to-noise ratio channels | Electricity | 103 | Active |
| US8599508B1 | Method and system for compensating for adjacent tracks during reading of data | Physics | 66 | Active |
| US9088300B1 | Cyclic redundancy check for out-of-order codewords | Electricity | 63 | Active |
| US8255763B1 | Error correction system using an iterative product code | Electricity | 55 | Active |
| US7072417B1 | LDPC encoder and method thereof | Electricity | 54 | Expired |
| US7000177B1 | Parity check matrix and method of forming thereof | Electricity | 54 | Expired |
| US8171309B1 | Secure memory controlled access | Physics | 53 | Active |
| US8300339B1 | Method and system for compensating for adjacent tracks during reading of data | Physics | 51 | Active |
| US7571372B1 | Methods and algorithms for joint channel-code decoding of linear block codes | Physics | 47 | Active |
| US7840878B1 | Systems and methods for data-path protection | Electricity | 47 | Active |
| US8219878B1 | Post-processing decoder of LDPC codes for improved error floors | Electricity | 47 | Active |
| US8423789B1 | Key generation techniques | Physics | 46 | Active |
| US8402217B2 | Implementing RAID in solid state memory | Physics | 43 | Active |
| US8255765B1 | Embedded parity coding for data storage | Electricity | 43 | Active |
| US8127209B1 | QC-LDPC decoder with list-syndrome decoding | Electricity | 42 | Active |
| US8504887B1 | Low power LDPC decoding under defects/erasures/puncturing | Electricity | 41 | Active |
| US8296637B1 | Channel quality monitoring and method for qualifying a storage channel using an iterative decoder | Electricity | 40 | Active |
| US6965652B1 | Address generator for LDPC encoder and decoder and method thereof | Physics | 40 | Expired |
| US8638513B1 | Method and system for compensating for adjacent tracks during reading of data | Physics | 38 | Active |
| US7941590B2 | Adaptive read and write systems and methods for memory cells | Physics | 36 | Active |
| US6504493B1 | Method and apparatus for encoding/decoding data | Physics | 34 | Expired |
| US8028216B1 | Embedded parity coding for data storage | Electricity | 33 | Active |
| US8351258B1 | Adapting read reference voltage in flash memory device | Physics | 32 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.