Method for optimizing a layout of supply lines
US7454720B2 · kind B2 · utility
1Cited by
2References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 16, 2005 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Jan 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for optimizing a circuit layout is provided which optimizes a circuit layout as a result of utilizing unused tracks of the circuit layout to expand supply lines. In a first step, a circuit layout is constructed by means of any circuit layout construction method, whereby requirements regarding the design of supply lines are reduced. Subsequently, in a second step, the method for optimizing a circuit layout is used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.