Method, apparatus and computer program product for optimizing an integrated circuit layout
US7454721B2 · kind B2 · utility
8Cited by
10References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2006 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Mar 2, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and computer program product for optimizing the layout of an integrated circuit design. Base ground rules and recommended ground rules are prioritized according to the impact they have on the yield of the integrated circuit design. The layout is optimized according to the prioritized base ground rules and recommended ground rules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.