Inventor · South Burlington, VT, US

Robert F. Walker

22Patents
8h-index
29Co-inventors
75Inventor score

Filing activity: Dec 17, 1982 → Aug 27, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US7302651B2 Technology migration for integrated circuits with radical design restrictions Physics 203 Expired
US7484197B2 Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs Physics 199 Active
US7503020B2 IC layout optimization to improve yield Physics 107 Active
US4516266A Entity control for raster displays Physics 11 Expired
US7363601B2 Integrated circuit selective scaling Physics 10 Expired
US7062729B2 Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization Physics 9 Expired
US7260790B2 Integrated circuit yield enhancement using Voronoi diagrams Physics 9 Expired
US7257783B2 Technology migration for integrated circuits with radical design restrictions Physics 8 Expired
US7454721B2 Method, apparatus and computer program product for optimizing an integrated circuit layout Physics 8 Expired
US7882463B2 Integrated circuit selective scaling Physics 7 Active
US7761821B2 Technology migration for integrated circuits with radical design restrictions Physics 6 Active
US7895562B2 Adaptive weighting method for layout optimization with multiple priorities Physics 5 Active
US8464189B2 Technology migration for integrated circuits with radical design restrictions Physics 5 Active
US7117456B2 Circuit area minimization using scaling Physics 5 Expired
US7610565B2 Technology migration for integrated circuits with radical design restrictions Physics 4 Active
US7735042B2 Context aware sub-circuit layout modification Physics 4 Active
US7120887B2 Cloned and original circuit shape merging Physics 4 Expired
US7568173B2 Independent migration of hierarchical designs with methods of finding and fixing opens during migration Physics 3 Active
US7818694B2 IC layout optimization to improve yield Physics 2 Active
US7865848B2 Layout optimization using parameterized cells Physics 2 Active
US11567945B1 Customized digital content generation systems and methods Physics 0 Active
US7752589B2 Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.