Methods and apparatuses for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs
US7454732B2 · kind B2 · utility
4Cited by
19References
36Claims
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Key dates
| Filing date | Oct 18, 2005 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Sep 2, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs are described herein. According to one embodiment of the invention, a hierarchical resource estimation is performed based on a technology independent register transfer level (RTL) netlist, which is to be partitioned between multiple ICs. Based on the estimation, the RTL netlist is partitioned between the multiple ICs. In response to the partition and the estimation, immediate feedback information is provided to a user.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.