Field effect transistor with raised source/drain fin straps

US7456471B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Brent A. Anderson · Jericho, US
• Thomas Ludwig · Sindelfingen, DE
• Edward J. Nowak · South Burlington, US

Key dates

• Filing date: Sep 15, 2006
• Grant date: Nov 25, 2008
• Expiry date: Oct 3, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/025

Abstract

Therefore, disclosed above are embodiments of a multi-fin field effect transistor structure (e.g., a multi-fin dual-gate FET or tri-gate FET) that provides low resistance strapping of the source/drain regions of the fins, while also maintaining low capacitance to the gate by raising the level of the straps above the level of the gate. Embodiments of the structure of the invention incorporate either conductive vias or taller source/drain regions in order to electrically connect the source/drain straps to the source/drain regions of each fin. Also, disclosed are embodiments of associated methods of forming these structures.