Electrostatic discharge device and method
US7456477B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2002 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Oct 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.