Package design and method of manufacture for chip grid array
US7456496B2 · kind B2 · utility
40Cited by
10References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 2005 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Oct 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.