Test structures and method of defect detection using voltage contrast inspection
US7456636B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2006 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Mar 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/307
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Test structures and a method for voltage contrast (VC) inspection are disclosed. In one embodiment, the test structure includes: a gate stack that is grounded by a ground to maintain the gate stack in an off state during VC inspection, which allows NFET defect detection using VC inspection prior to contact dielectric deposition. The test structure may alternatively include a gate stack that is biased by a bias to maintain the gate stack in an on state during VC inspection. The method may detect source-to-drain shorts in a transistor using VC inspection by providing a gate stack over a source and drain region of the transistor that is grounded by a ground to maintain the gate stack in an off state during VC inspection; and inspecting the transistor using voltage contrast. If the drain of the NFET brightens during VC inspection, this indicates a source to drain short.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.