Method and apparatus for a programmable level translator
US7456654B1 · kind B1 · utility
5Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2006 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Dec 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level translator includes a programmable booster stage that augments the drive level of the level translator under certain conditions. The booster stage is programmably activated. e.g., via a memory cell or control bit, and augments operation of the pull-up stages of a cross-coupled latch within the level translator. When the voltage levels at the high voltage portion of the level translator are reduced below a threshold voltage, the booster stage is activated to maintain proper operation of the level translator despite the reduced voltage levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.