Memory device and method for verifying information stored in memory cells
US7457144B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2006 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Oct 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises a plurality of first and second non-volatile memory cells arranged as an array. Each memory cell stores information. The memory device further comprises an access unit coupled to the array. The access unit stores information in the plurality of first and second non-volatile memory cells. The memory device further comprises a verifying unit coupled to the array. The verifying unit verifies the information stored in a group of the first and second memory cells by verifying only a subset of the group. The subset comprises at least one of the second memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.