High density memory array system
US7457154B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2006 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Nov 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/694
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system comprising a memory array having a plurality of memory units, a column decoder, a row decoder, a selecting/driving circuit and a sensing circuit is disclosed. Each memory unit comprises a gate electrode coupled to a word lines, a source region coupled to a source line or a first bit line, a drain region coupled to a drain line or a second bit line, a first spacer between the source region and the gate electrode and a second spacer between the drain region and the gate electrode. When a first-bit program operation is performed on the memory unit, a switch-on signal is applied to the gate, a programming signal is applied to the source region and the drain region is switched to ground. As the memory unit is activated, the carriers are injected and stored in a first spacer, thus represents a first bit in the memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.