Resistance change memory device
US7459715B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2007 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Jun 11, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S439/936
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, bit lines and word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings connecting bit lines to the read/write circuit; and third vertical wirings connecting word lines to the read/write circuit, wherein the memory cell includes a variable resistance element. The variable resistance element has: a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and electrodes formed on the opposite sides of the recording layer, one of the electrodes serving as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.