Device containing isolation regions with threading dislocations

US7459731B2 · kind B2 · utility

Assignee

• The Regents of the University of California · US

Inventors

• Ya-Hong Xie · Flemington, US
• Tae Sik Yoon · Seoul, KR

Key dates

• Filing date: Aug 30, 2006
• Grant date: Dec 2, 2008
• Expiry date: Jan 6, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An article of manufacture includes a substrate, a relaxed buffer layer disposed on the substrate, and a plurality of isolation regions formed in the relaxed buffer layer. The isolation regions include threading dislocations while the remainder of the relaxed buffer layer is substantially free of threading dislocations. The relaxed buffer layer may be formed from silicon germanium while the substrate may be formed from silicon. A capping layer may be disposed over the relaxed buffer layer.