Method and apparatus for power efficient and scalable memory interface
US7459938B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2006 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Sep 8, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Transmission of digital signals across a bus between an electronic device having a transmitter and another electronic device having a receiver with termination for both the transmitter and receiver being referenced to ground, such that the electronic device having the transmitter and the other electronic device having the receiver are able to be powered with differing decoupled voltages, such that the voltage employed by the electronic device having the transmitter is able to be lower than the voltage employed by the other electronic device having the receiver, and wherein the electronic device having the transmitter may transmit addresses and/or commands to the other device having the receiver using single-ended signaling, while both electronic devices may exchange data using differential signaling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.