Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications
US7459958B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2006 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Nov 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.