Method and apparatus for reducing leakage current in a read only memory device using shortened precharge phase
US7460424B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jan 3, 2007 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Jan 19, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by reducing the duration of the precharge cycle during each read cycle so that the associated leakage current will flow for a shorter time period during each cycle. The precharge phase is positioned at the beginning of each read cycle, prior to the evaluation phase. The precharge phase is terminated by a subsequent clock edge or by an internal time out prior to a subsequent clock edge. The time interval between when the columns reach their precharge voltage and the evaluation phase begins is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.