Segmented on-chip memory and requester arbitration
US7461191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2005 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Dec 20, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S370/913
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory access technique is provided that may be used in WLAN (Wireless Local Area Network) communication devices. An on-chip memory has multiple memory circuits forming individually addressable memory segments. An arbitration unit arbitrates between multiple requesters, each requesting access to the on-chip memory. The requesters are on-chip circuits and/or external devices. The arbitration unit determines a memory circuit to be accessed for each request that is received from a requester. The determination may be based on a software configurable arbitration scheme. The memory segments may form a bank of single-port SRAM (Static Random Access Memory) devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.