Method of fabricating a bipolar transistor having reduced collector-base capacitance

US7462547B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Hiroyuki Akatsu · Yorktown Heights, US
• Rama Divakaruni · Ossining, US
• Marwan H. Khater · New York, US
• Christopher M. Schnabel · Poughkeepsie, US
• William R. Tonti · South Burlington, US

Key dates

• Filing date: Dec 4, 2006
• Grant date: Dec 9, 2008
• Expiry date: Dec 4, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/137

Abstract

A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.