Semiconductor package having a grid array of pin-attached balls
US7462783B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2004 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Jan 29, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor chip (1101) of a ball grid array device (1100) is mounted onto tape substrate (1102) using attach adhesive (1103). The metal layer on the top surface of substrate (1102) uses between about 30% to 90% of its area for connecting lines (1104), and only the remainder for members/rings (1105) and terminals (1106). Routing of differential pair signals and large numbers of signals on a single layer tape package are feasible. This embodiment creates an inexpensive high performance tape ball grid array package for chip-scale devices. Terminals (1106) serve the connection (by bonding wires or reflow bumps) to the chip contact pads. Inserted in members/rings (1105) are the conductive pins (1107), which serve as anchors for the solder bodies/balls (1108). Pins (1107) are substantially insensitive to the thermomechanical stresses, which occur in device (1100) during assembly, testing and operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.