ESD structure for high voltage ESD protection
US7462885B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2006 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Feb 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
An electrostatic discharge-protected MOS structure is disclosed. An electrostatic discharge-protected MOS structure includes a semiconductor substrate of a first type, a first well of the first type formed in the semiconductor substrate, and a second well of a second type disposed adjacent to the first well. The MOS structure further includes a source region, a drain region, and an oxide layer and a polysilicon layer for forming a gate electrode of the MOS structure. In addition, the MOS structure includes a parasitic SCR comprising at least a parasitic NPN bipolar transistor and a buried layer of the second type interposed between the second well and the semiconductor substrate. The buried layer functions to lower a resistance of the semiconductor substrate during an ESD event so that ESD currents generated by the parasitic SCR are dissipated through the buried layer and the semiconductor substrate, thereby protecting the MOS structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.