Writeable shift register lookup table in FPGA with SRAM memory cells in lookup table reprogrammed by writing after initial configuration
US7463056B1 · kind B1 · utility
20Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2005 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Jan 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An FPGA system includes a combined shift register and look up table (LUT) forming a shift register LUT (SRL) that provides data write, reset and shift enable on a cell-by-cell basis. The data write and reset can be performed during FPGA operation without requiring a number of frames or columns of configuration memory cells to be reprogrammed, as with conventional SRAM cells. The shift enable provides for synchronization to facilitate the cell-by-cell write and reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.