Patterned magnetic layer on-chip inductor
US7463131B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2005 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Aug 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An on-chip inductor structure includes top and bottom metal plates that are formed to surround a conductor coil formed between the top and bottom plates, but is separated therefrom by intervening dielectric material. The top and bottom plates are preferably formed from a ferromagnetic alloy, e.g. Permalloy, and are subdivided into a plurality of space-apart segments, thereby reducing eddy currents. The number of segments is optimized based upon the process technology utilized to fabricate the structure. Preferably, a finite gap is formed between the top plate and the bottom plate, the height of the gap being chosen to adjust the total inductance of the structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.