Method and apparatus for supporting opportunistic sharing in coherent multiprocessors
US7464227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2002 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Dec 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for improved cache performance is disclosed. In one embodiment, a processor with a cache having a dirty cache line subject to eviction may send the dirty cache line to an available replacement block in another processor's cache. In one embodiment, an available replacement block may contain a cache line in an invalid state. In another embodiment, an available replacement block may contain a cache line in an invalid state or in a shared state. Multiple transfers of the dirty cache line to more than one processor's cache may be inhibited using a set of accept signals and backoff signals. These accept signals may be combined to inhibit multiple processors from accepting the dirty cache line, as well as to inhibit the system memory from accepting the dirty cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.