High performance serial bus testing methodology

US7464307B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jay Nejedlo · Wilsonville, US
• Mike Wiznerowicz · Beaverton, US
• David G. Ellis · Tualatin, US
• Richard Glass · Olympia, US
• Andrew Martwick · Folsom, US
• Theodore Z. Schoenborn · Portland, US

Key dates

• Filing date: Mar 25, 2003
• Grant date: Dec 9, 2008
• Expiry date: Jul 9, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L1/242
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.