Integrated circuit capable of locating failure process layers
US7464357B2 · kind B2 · utility
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3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2006 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Feb 18, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31855
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.