Integrated circuit packages with reduced stress on die and associated methods
US7465651B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2005 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Mar 12, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Mechanical stresses are reduced between an electronic component having relatively low fracture toughness and a substrate having relatively greater fracture toughness. In an embodiment, the component may be a die having mounting contacts formed of a low yield strength material, such as solder. A package substrate has columnar lands formed of a relatively higher yield strength material, such as copper, having a relatively higher melting point than the component contacts and having a relatively high current-carrying capacity. The component contacts may be hemispherical in shape. The lands may be substantially cylinders, truncated cones or pyramids, inverted truncated cones or pyramids, or other columnar shapes. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.