High performance CMOS device design
US7465972B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2005 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Apr 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/017
Abstract
A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.