Semiconductor die structure featuring a triple pad organization
US7466013B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 2005 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Dec 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12044
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die featuring vertical rows of bonding pad structures is disclosed. The rows of bonding pad structures are located vertically in the Y direction, or traversing the width of the semiconductor die. A vertical row of bonding pad structures is located on each side of the semiconductor die while a third vertical row of bonding pad structures is located in the center of the semiconductor die. A first set of wire bonds connect each bonding pad structure located on the sides of the semiconductor die to a conductive lead structure located on a ceramic package. A second set of wire bonds connect each bonding pad structure located in the center of the semiconductor die to a lead on chip (LOC) structure located on the semiconductor die. The configuration of only vertical rows of bonding pad structures allows optimized parallel testing of the completed semiconductor chip to be accomplished when compared to testing performed on a semiconductor chip featuring both vertical and horizontal rows of bonding pad structures located on all sides of the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.