MEMS device wafer-level package
US7466018B2 · kind B2 · utility
5Cited by
39References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2007 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Jun 19, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method and system in which a semiconductor wafer having a plurality of dies is inspected through a visual inspection and/or an electrical test. If certain of the dies on the wafer pass the inspection, then windows are mounted or affixed above those certain dies while they are still a part of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.