Semiconductor storage device having a plurality of stacked memory chips
US7466577B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 30, 2006 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Dec 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L24/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor storage employs a base substrate (101) having a command/address external terminal group (CA), a data input/output external terminal group (DQ), and a single chip select external terminal (CS), and also comprises a plurality of memory chips (110) to (113) mounted on a base substrate (101), each of which can individually carry out read and write operations. The terminals (CA), (DQ), and (CS) are connected to an interface chip (120). The interface chip (120) has a chip select signal generation circuit that can individually activate a plurality of memory chips (110) to (113) on the basis of an address signal fed by way of the terminal (CA) and on the basis of a chip select signal fed by way of the terminal (CS).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.