Self-boosting method for flash memory cells
US7466590B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2005 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Dec 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low voltage (e.g. of the order of or one to three volts) instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a flash device such as a NAND flash device and one or more additional word lines next to such word line to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes. In a modified erased area self boosting scheme, low voltages are applied to two or more word lines on the source side of the selected word line to reduce band-to-band tunneling and to improve the isolation between two boosted channel regions. In a modified local self boosting scheme, zero volt or low voltages are applied to two or more word lines on the source side and to two or more word lines on the drain side of the selected word line to reduce band-to-band tunneling and to improve the isolation of the channel areas coupled t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.