Memory access system and method using de-coupled read and write circuits
US7466607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Feb 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A de-coupled memory access system including a memory access control circuit is configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference and a read signal for generating a read enable signal, and a write initiate circuit responsive to the second time reference and a write signal for generating a write enable signal independent of the read enable signal for providing independent, de-coupled write access to a memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.