Arrangement and method for controlling communication of data between processors
US7467312B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2005 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Jan 31, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The communication of data between two coupled processors is controlled using a ready-to-receive signal which is provided by the first processor such that it has an activated signal level or a deactivated signal level and which is used to indicate to the second processor that the first processor is or is not ready to receive data. The second processor is able to change from the awake state to a sleep state and to change back from the sleep state to the awake state. The second processor detects when the first processor changes the ready-to-receive signal from the deactivated signal level to the activated signal level while the second processor is in the sleep state and, in this case, determines that the changing of the ready-to-receive signal is a request to change to the awake state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.