Ethernet media access controller embedded in a programmable logic device—clock interface
US7467319B1 · kind B1 · utility
7Cited by
45References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2005 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Jan 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0697
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock interface for a media access controller in a programmable logic device is described. The media access controller includes a clock generator for providing a clock signal to configured configurable routing of the programmable logic device to obtain a loaded version thereof. The loaded clock signal is provided to a clock network of the media access controller and to a delay cell of the media access controller to obtain an indication of the loading by the user instantiated design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.