Circuit for and method of generating a delay in an input/output port of an integrated circuit device
US7468616B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2006 |
| Grant date | Dec 23, 2008 |
| Priority date | — |
| Expiry date | Jan 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for generating a delayed output in an input/output port of a device adapted to implement circuits operating on a range of voltages is disclosed. The circuit comprises a first terminal of a delay stage of said input/output port coupled to receive a signal to be output by the circuit; a first pass gate coupled to the first terminal; a capacitor having a first terminal coupled to the output of the first pass gate and a second terminal coupled to ground; a second pass gate coupled to the first terminal of the capacitor; and a second terminal of said delay stage of said input/output port coupled to the second pass gate and outputting a delayed signal based upon the second pass gate. A method of generating a delayed output in an input/output stage of a device adapted to implement circuits operating on a range of voltages is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.