High-definition de-interlacing and frame doubling circuit and method
US7468754B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2005 |
| Grant date | Dec 23, 2008 |
| Priority date | — |
| Expiry date | Apr 6, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S348/911
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A combined de-interlacing and frame doubling system (114, 114′ and 114″) advantageously serves to de-interlace successive lines of Present Field Video data at twice the field rate to yield an output bit stream suitable for display on display device that utilizes progressive scanning. The de-interlacing and frame doubling system in accordance with present principles includes a frame memory mechanism (116, 116′ and 116″) for storing at least one frame of interlaced video having a prescribed field rate. At least one de-interlacing circuit (11401, 1140′1, 1140″) pulls at least two fields of video data from the memory mechanism at a rate of at least twice the field rate for performing a full de-interlacing function in half of a field period to generate the a progressive, frame doubled signal for receipt at the display device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.