Asymmetrical bus
US7469311B1 · kind B1 · utility
52Cited by
0References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2006 |
| Grant date | Dec 23, 2008 |
| Priority date | — |
| Expiry date | Dec 19, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional sub-link and a downstream unidirectional sub-link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.