Patent · US Active

Scan sequenced power-on initialization

US7469372B2 · kind B2 · utility

6Cited by
10References
13Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 4, 2006
Grant dateDec 23, 2008
Priority date—
Expiry dateMay 3, 2027

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/318575
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A scan sequenced initialization technique supplies a predefined power-on state to a device or module without using explicit reset input to the registers. This technique supplies a predefined pattern to parallel scan chains following power-on reset. The predefined pattern places the device or module in a architecturally specified reset state. The parallel scan chains are required for structural manufacturing test. Once the power-on reset scanning is complete, the power-on reset sequencer indicates completion of state initialization to other circuits.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.